PA3FWM's software defined radio page

Since summer 2004, I have been experimenting with the new way of building a radio receiver known as "software-defined radio". This page gives some information about this project.
Updated February 2005
Updated October 2005
Updated January 2006
Updated February 2006
Updated June 2006
Updated June 2007
Updated June 2008
Updated November 2008
Updated May 2009
Updated April 2013

What is Software-Defined Radio?

Traditionally, radio receivers were built using analog hardware, like capacitors, coils and quartz crystals for filtering, and a diode as a detector. However, by converting analog signals to digital ones, one can replace part of this signal processing by a computer program operating (i.e., doing calculations) on the digital signals.

This is what software-defined radio (SDR) is all about: implementing a radio receiver (and transmitter) in software (as much as possible). Such a radio receiver could in principle perform much better than an analog one, because filters can be made much closer to ideal (steep slopes, high rejection of unwanted signals) and advanced algorithms can be invented an implemented to do things that are not so easy in analog hardware (e.g., automatically tuned notch filters).

Ultimately, one might build a radio receiver consisting of just a very good analog-to-digital converter connected directly to the antenna, and a powerful computer. However, at the present state of the technology, this is not yet feasible: the available analog-to-digital converters are either not fast enough to handle e.g. the entire short-wave spectrum of say 0...30 MHz, or don't have enough dynamic range to handle the wide variety of signal strengths in that spectrum. So some more analog hardware is still needed to feed only part of the spectrum to the computer.

Hardware

The first hardware I used was rather simple. It is in fact two direct conversion receivers with 90 degrees phase difference, feeding the left and right input channel of the (stereo) soundcard in my PC.
The local oscillator is simply a crystal oscillator at 4 times the desired receive frequency, followed by a two flip-flop circuit to divide the frequency by four and produce the 90 degrees phase difference between the two signals. So using a 28.322 MHz crystal oscillator (commonly found in computer junk, since it used to be used as a pixel clock in VGA cards) ends up nicely in the 40 meter band (7080.5 kHz).
The soundcard samples the signal at 48 kHz, allowing input signals up to half this, i.e., 24 kHz. Thus, in this example signals between 7080.5 - 24 and 7080.5 + 24 kHz can be accepted. The use of two signals with 90 degrees phase difference (also known as in-phase (I) and quadrature (Q) signals) allows the software to distinguish between signals that are above the local oscillator frequency and those below, even though they produce the same frequency range at the output of the mixer.
This hardware is mostly identical to the hardware described in AC50G's article in QEX July/August 2002.

Here's a picture of the hardware (click for a larger version; thanks to PE1NUT for many hardware photographs on this page).
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The above hardware is nice for lots of initial experiments, but has some severe limitations: it's bound to a couple of available crystal frequencies, has limited dynamic range (my soundcard is a 16-bit card), and only covers 48 kHz of spectrum.
I have started developing new hardware, with the following aims:

• External A/D converter, with 24 bits resolution (thus larger dynamic range) and about 192 kHz sample rate (thus covering a larger bandwidht). Soundcards with these specifications are very rare, and having the A/D converter near the antenna rather than inside the (noisy) PC is probably also a good idea.
• Connection to the PC using ethernet. The above-mentioned A/D-converter produces 24 bits/sample * 192000 samples/sec * 2 (I and Q channel) = 9.216 Mbit/sec. The easiest way to feed this to the PC seems to be by converting it into 10 Mbit/s ethernet frames. (USB would also be nice, but is much more complicated.)
• Fully tuneable in steps of about 25 kHz. This could be done by using a DDS (direct digital synthesizer), but for the moment I intend to build a regular PLL with a 1:2 tuning range followed by a circuit that divides this by a user-selected power of 2.
• Preselection. This is desirable because the mixer I'm using receives on all odd harmonics of the local-oscillator frequency...

Here's a picture of the new hardware in its October 2004 state of assembly:
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[see update]

Software

I'm writing the software from scratch, since this is in fact the most interesting part of the project. In October 2004, the software provided a 48 kHz spectrum display, a 48 kHz waterfall display (comparable to the 3 kHz wide waterfall found in typical PSK-31 software), and a tunable "demodulator". The latter simply is a software implementation of what would be an IF filter, a product detector and a BFO in a hardware implementation: basically, an SSB or CW demodulator. The output of this demodulator is fed to the output part of the soundcard, so one can actually listen to the received signals.

Some examples

The 48 kHz wide waterfall display provides for some interesting views of what happens on the bands. Here are a few examples:

The above picture shows a part of the 40 meter band (click on it for a larger version).

One sees several SSB stations operating (e.g. a strong one at 7068 kHz). The white horizontal line at 7084 kHz indicates the passband of the demodulator, in this case tuned to one of the weaker SSB stations with 3 kHz bandwidth.

Furthermore, someone seems to be testing his/her antenna by sweeping, his/her transmitter over the band...

This picture was made with the receiver centered on 1000 kHz, in the medium wave broadcast band.

One clearly sees the strong signal of "Radio 10 Gold" on 1008 kHz. Note the carrier and the sidebands on both sides of it. It seems that the transmitter is modulated with audio up to 6 kHz, even though only 4.5 kHz is allowed by the (European) channel spacing of 9 kHz. Another broadcaster is visible at 1017 kHz, and at 990 kHz two AM carriers interfere which each other.

At the left, several morse signals are visible. Presumably, these are hams operating in the 40 meter band, which is happily received at the 7th harmonic of the LO. (The Tayloe detector receives at all odd harmonics of the local oscillator, and my circuit does not have any preselection yet).

Finally, two dots are visible at 996 kHz: this is the Russian time signal station at 4996 kHz, being received at the 5th harmonic...

Update February 2005

New hardware working

At the top left is a preliminary version of the VCO. In a later version, it should cover 60 - 120 MHz. It is tuned in 100 kHz steps with a MC145170-based PLL, at the bottom left. Immediately to the right of the PLL is the programmable octave divider, which divides the VCO signal by 2² to 2¹⁰, thus allowing a final tuning range of 58 kHz to 30 MHz. Note that the VCO's signal must be divided by at least 4 in order to generate the quadrature signals for the mixer.

The mixer is again the well-known Tayloe circuit. The antenna signal comes in through the BNC connector at the top, via a transformer (on the blue toroidal core) for symmetry. The mixer has differential outputs, which fits fine with the analog to digital converter's differential inputs. A total of four amplifiers are thus needed: two each for the I and Q signals. The analog-to-digital converter is a PCM1804.

At the right, a microcontroller (ATmega32) is found. Its main responsible is converting the serial data stream coming out of the AD converter to something that resembles a 10 Mbit/s ethernet frame, by doing some buffering and adding an ethernet header. The serial data speeds are too high to be processed directly, so two shift registers and some timing logic are provided so the processor can handle the data as bytes rather than individual bits. Unfortunately, the microcontroller does not have enough processing power to calculate the ethernet CRC, so the ethernet frames contain a bogus value in the CRC field. In order to receive these frames, the ethernet card in the PC has to be programmed to ignore the CRC; unfortunately, not all ethernet chipsets allow this. (NE2000 clones do, but present a rather high CPU load; 3C905 doesn't; RTL8139 does, but garbles about half the frames in a deterministic way, so some extra code is needed to un-garble them. Yes, this ugly. An implementation on an FPGA would be nicer: no external shift registers needed, and a CRC generator could be added easily.)

At the top, some hay-wired components are visible that produce a nice symmetrical ethernet signal suitable for transmission over a UTP (or FTP) cable. The block labelled "Fil-Mag" is a potted low-pass filter and transformer, salvaged from an old ISA ethernet card. This transformer block is quite essential to ensure symmetry of the UTP signal so it doesn't radiate too much.

In order to tell the microcontroller how to program the PLL and octave divider, a data stream from the PC to the microcontroller is also needed. This reverse data stream is provided by using the ethernet in full-duplex mode. The data is transported using RS232 frames, with one byte per ethernet frame, by interpreting the ethernet signal as a frequency-modulated carrier. The frequency-demodulation is done by a single IC, and the output is fed into the microcontroller's USART. The microcontroller definitely wouldn't be fast enough to handle the 10 Mbit/s directly, and we don't need nearly that much throughput anyway, so this hack is quite useable.

The main hardware job still to be done (besides fixing the VCO tuning range), is shielding and decoupling. It seems quite a bit of noise is leaking from the digital circuitry around the microcontroller into the analog circuitry. This is not unexpected of course, and I already kept it in mind while laying out the circuit board.

Software

Here's an example of an almost 200 kHz wide view of the 80 meters band, apparently during an RTTY contest (between 3570 and 3600 kHz):

Note that the noise floor increases at the lowest and highest frequencies; this is a property of this A/D converter (it is a sigma-delta converter, and the noise shaping used does not completely move the noise out of the pass band at this high sample rate).

Here is another example, of the 40 m band; note the strong AM broadcasters just above 7100 kHz:

Note that some of the AM carriers above 7100 kHz are also weakly visible at the image frequency, e.g. at 7030.8 kHz; better balancing the I and Q channels (making gain and phase shift equal) should reduce this.

Update October 2005

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Furthermore, some shielding has been inserted, right across the A/D converter, as shown above. The purpose of this was to prevent noise from the digital part from entering into the analog part, but this is not very successful. In fact, it is unclear what route this noise takes, but it sure doesn't seem to be blocked by this new shield. The noise is only there when I connect an actual antenna instead of a signal generator, and decreases when there is no direct connection between the coax cable's shield and the ground of my hardware. Its level varies with what ethernet port of my PC I connect the system to, presumably due to a difference in termination (perhaps some ports are more symmetrical than others). This suggests that the noise is simply radiated by the ethernet cable, and picked up by the antenna; however, a simple portable radio kept near the antenna is not affected by the noise, contradicting this hypothesis...

Resolving the noise problem is probably the last thing I'll do with this hardware. I have been pointed to some very nice new A/D converters having a 2.5 MHz sample rate, with the same dynamic range as my present converters. So I've started playing with FPGAs (using a Xilinx Spartan-3 development kit), and hope to start designing new hardware soon around these new A/D converters and an FPGA to convert their output to a 100 Mbit/s ethernet signal.

At the UKW-Tagung Weinheim I gave a talk on my project. The accompanying text in the "Scriptum" can be found here (in german!).

Update January 2006

At the turn of the (UTC) year, I used my SDR hardware to record how several long-wave time signal transmitters transmitted the leap second; the results are shown here.

Apart from that, I've been busy designing and building new hardware, with AD7760 2.5 Msamples/second A/D-converters and a Xilinx Spartan-3 FPGA. The prototype has now been built partially (i.e., no mixer yet and only 1 A/D converter) and works, providing me with direct reception of the entire spectrum between 0 and 1 MHz.
Before continuing building, I'm now redesigning the software. It used to use just one FFT to go directly from the input signal to a spectrum with 50 Hz resolution. My computer however isn't fast enough to do that at 2.5 Msamples/sec, so more efficient algorithms are needed.

Pictures of the new hardware will be added later...

Update February 2006

Here's a photograph of the new hardware:

Reflecting on this project, I'm somewhat (but happily) surprised at how feasible it is for a hobbyist to work with these modern parts such as A/D converters, FPGAs and 0603 SMD components.
The 0.5 mm grid of the IC pins is not a problem: "kitchen-table" etching techniques turn out to be good enough for producing 0.25 mm wide traces at 0.25 mm spacing. In fact, the board looks so good that I think 0.20 mm and perhaps even 0.15 mm would still be feasible (for comparison: commercial PCB manufacturers typically specify between 4 and 8 mil as a minimum track width, i.e. 0.1 to 0.2 mm).
Furthermore, datasheets of modern chips tend to assume that they will be mounted on a 4- or even 6-layer printed circuit board, which of course is not something a hobbyist can manufacture. My board however is essentially a single layer (the back side is full copper for shielding), with some extra wiring added by hand (mostly power supply and a few clock signals). This works fine.
One might expect noise levels to be higher due to the fact that e.g. decoupling capacitors are positioned further away from the chips than on a multi-layer board. Indeed, preliminary measurements of the A/D converter's output noise level indicate it is about 2 dB higher than the datasheet specifies. However, this may also be due to a lack of shielding and the fact that for simplicity I have not yet added separate voltage regulators for the analog and digital parts of the circuit.

Since the photograph was taken, the second A/D converter and the second ethernet PHY chip have been added. Next in line are the mixer and low-pass filters between mixer and A/D converters.

Update June 2006

After adding the mixer and low-pass filters I could finally receive a 2.5 MHz bandwidth anywhere in the shortwave spectrum. However, the original structure of the software did not scale to such a high bandwidth (implying a high data rate): it used a single windowed FFT, with a bin size on the order of 50 Hz for all spectrum and waterfall displays and as a starting point for filtering and demodulation; however, this approach is very inefficient (way too slow on my PC) for a 2.5 MHz bandwidth. Therefore, I restructured the software, so it now uses an initial 8192 non-windowed FFT, after which filtering and decimation reduce the data rate for further processing, which again may involve several more FFTs.

A screenshot of the new software is given below. (click on it to magnify). The centerfrequency is 6842 kHz, and the upper spectrum and waterfall show the full 2.5 MHz bandwidth; most noticable are the strong broadcast signal around 6000 kHz, and about 7100 kHz. Clearly, a 2.5 MHz bandwidth is way too much to see details (such as modulation sidebands) of the individual signals, so zooming is needed. An 80 kHz wide zoomed spectrum and waterfall display are shown in the lower half of the screen, showing most of the (old European) 40 m amateur band. The band plan seems to be well obeyed: morse code below 7040 kHz, and LSB above. Note the slanted line, visible in both waterfall displays: I guess this is one of the ionospheric "chirp sounders" that transmit a continuously increasing frequency to measure the ionosphere; however, those sounders are said to use a 100 kHz per second rate, whereas this signal seems to rise by about 122 kHz/s.

Next, it was time to solder the last parts of the hardware: the second FPGA and the D/A converter for the transmitter. The board now looks like this (refer to the earlier picture for annotations):

The hardware is now essentially finished; the open places on the board are for such non-essential items as more voltage regulators and the configuration memory for the FPGAs (for the moment, I reprogram them everytime from my PC through the header in the center of the board).
Cooling is a problem: the A/D and D/A converters each consume and dissipate on the order of a watt of power. They have a metal surface at their bottom, which the manufacturer says should be soldered to the circuit board for cooling; however, that's not something I can do. So I drilled holes in the board (before mounting the chips, of course!), and try to drain the heat through screws mounted in these holes; so far, the chips survive, but they still are too hot to comfortably touch for a long time.

With the D/A converter in place, making a two-way QSO should be within reach. This required writing some more code (both for the FPGA and the PC). After an unsuccesful attempt a week earlier, the first QSO was made on June 29th; I talked to PI4THT, the university club station located about 1 km from my house. Here's a screenshot:

The upper half again shows a 2.5 MHz wide spectrum, the lower half is a zoomed display with a width of about 19 kHz. Halfway the time of this diagram, the transmitter was switched on; so the weak signal at the top of the lower waterfall is PI4THT, and the strong garbage at the bottom is my own transmitted signal as received by my own receiver.
The contact was made on 21 MHz, at a time when that band was not open. The transmit power was very small, less than 1 mW: I simply connected the dipole antenna directly to the output of the D/A converter; I haven't yet built a power amplifier. The lack of propagation and my low transmit power are the only excuses I can offer for transmitting such a dirty signal: as can be seen in the upper waterfall, every now and then I transmitted garbage of several hundred kHz wide. Presumably, this is caused by the data buffer in the transmit FPGA over- or underrunning when the PC does not supply data regularly enough. This, and several other issues such as the inadequate sideband filtering still need to (and will) be addressed; but for the moment, I'm quite happy with this first QSO!

Update June 2007

A new piece of hardware has been built, containing a new A/D-converter which should be good enough to sample the entire short-wave spectrum at once! After comparing several A/D-converter chips' specifications, I selected (like several other amateur radio SDRs) the LTC2208. This chip has a maximum sample rate of 130 MHz, produces 16 bits per sample, and has a few other nice features such as randomizing and dithering. Unfortunately, it is quite hard to solder, because it comes in a package without pins; fortunately, a technician in the electrical engineering department of the University of Twente (my employer) could help me with this using a stereo microscope.

Since I didn't feel like building another complete board with an FPGA, ethernet drivers, voltage regulators etc., I decided to put the LTC2208 on a small "daughter board" connected to my previous board. I disabled the outputs of the AD7760s on that board through their chip select pins, so I could connect the LTC2208 to the same pins of the FPGA. The result is not beautiful and mechanically not very stable, but it saved me a lot of building work. It looks like this:

And it actually works! For the time being, the ADC is clocked at 40 MHz because that's the clock frequency that was already available on the board, so only 20 MHz of spectrum can be received now. Here's a preliminary picture of the entire spectrum between 0 and 20 MHz:

One readily readily recognizes the heavily used broadcast bands between 0.5 and 1.6 MHz, around 6 MHz, above 7.1 MHz, below 10 MHz, etc. The peak around 17 MHz, and other similar signals, are almost surely FM broadcast signals in the 88 - 108 MHz range, being aliased into the 8 - 20 MHz range.

16 bits at 130 MHz is more than 2 Gbit/s worth of data. That's way too much data to transport continuously to the PC through the two 100 Mbit/s ethernet interfaces on my board. The above picture was made by first storing 12288 samples in the FPGA's RAM, and then transporting that data "slowly" to the PC. Next job is to program the FPGA to filter out one or more pieces of the entire spectrum and send those parts to the PC continuously.

Update June 2008

I haven't updated this page for a long time, but that doesn't mean I didn't work on SDR related projects!

My most visible recent development is the WebSDR, an SDR receiver that can be controlled by multiple users simultaneously via the internet. The test setup is available at http://websdr.ewi.utwente.nl:8901.

Work on the direct-sampling hardware also continued. I wrote FPGA code for it to act as a digital downconverter, allowing me indeed to listen to radio signals.

However, it turns out that the noise level is way too high, as soon as anything resembling an antenna or even a coaxial cable is connected to the ADC input. This is almost surely due to the rather, ehm, amateuristic way in which it was built, with the ADC residing on a separate daughter board and lots of wires carrying high-speed digital signals hanging in the air between the two boards.

Therefore, I'm designing (and will soon start building) a new board, containing both the high-speed ADC and the FPGA (and ethernet etc.); this time, it will be a true double-sided board with vias, which unfortunately means I can't etch it myself...

Update November 2008

In the mean time, the new hardware discussed above has been built and is working! Here's a picture of the board in its present state:

The big square chip with 208 legs in the middle is the FPGA, a Spartan XC3S500E; this was the largest non-BGA FPGA that I could find. I don't really need so many I/O connections, but I do need the large amount of configurable logic inside.

Immediately to the right of the FPGA is the A/D converter, an LTC2216, clocked at 77.76 MHz. That's somewhat slower than last year's design, but still fast enough to sample the entire shortwave range at once. The A/D converter comes in a QFN package, which has no legs, only soldering pads on the bottom. Soldering this package proved rather difficult last year, so I decided to mount it upside-down this year, and solder thin wires to the pads. Unfortunately, this wasn't easy either, although it does work. It looks like this:

Note that the wires may look thick, but they are 0.2 mm diameter, soldered in a 0.5 mm grid.

Signals reach the A/D converter via the BNC connecter at the far right on the board. The gray box in between is a transformer used as a balun.
The 128-pin chip to the lower left of the FPGA is a Gigabit ethernet chip for sending data to the PC; the RJ45 connector is the metal thing at the far lower left of the board.

Some extensions are planned. Just above the FPGA is a small audio D/A-converter, intended to make the board work as a stand-alone digital shortwave radio. To the right of it, there's room for a fast D/A converter to use the board for transmitting. To the left of the FPGA there's room for a 512 kbyte memory chip, and there some FPGA pins are accessible for other extensions. The other chips on the board are voltage regulators, configuration memory and clock oscillators.

I haven't just built it, it actually works! And fortunately it looks like the noise levels is now indeed as low as it should be, in contrast to last year's hardware. On the lower shortwave bands, where atmospheric noise is rather high, the receiver can be connected directly to the antenna; for the higher bands I'll need to build a preamp. The dynamic range also seems to be largely sufficient: connected directly to my 40m dipole, only about a tenth of the ADC's input range is used, so there's still room for up to 20 dB of preamplification. However, more linearity tests are needed.

For shortwave listening, I programmed 4 digital down converters into the FPGA (and hope to add more in the future, if it still fits). This allows a PC connected to the board to receive up to 4 segments of between 150 kHz and 1.2 MHz bandwidth, each freely tunable to anywhere in the shortwave spectrum. One possible use of this is for the WebSDR project: 4 complete shortwave bands could be received with just a single board.

The board has not just been used for shortwave listening; it also has recently been used at the 25m Dwingeloo radio telescope to receive pulsars: pulsating radio sources in outer space.

Update May 2009

Over the past half year, the SDR hardware has been extended with a transmit section, built into a tin enclosure for robustness and shielding, and used for several experiments.

The most visible experiment has been its use at a WebSDR allowing a hundred or more people to use it simulatenously. This was first done between 24 and 30 December, see here for a report, and once again starting on May 10. The FPGA is programmed to simultaneously filter out up to (by now) 8 band segments of between 150 kHz and 1.2 MHz wide, which are then processed further (for the individual listeners) in the WebSDR server PC.

During the leapsecond at the end of 2008, I used the hardware to simultaneously record several broadcast bands; see the report here.

Next, I built the transmit section of the board (i.e., I soldered the DAC and some associated passive components onto the board), built the board into a tin enclosure (for robustness and shielding), and built a small power amplifier. With this equipment, I could make a first QSO on 40 m with a station in Munich, Germany; unfortunately, the report was only "44"; apparently, there was a bug somewhere causing my modulation to be rather distorted.
The equipment for this QSO looked like this:

The tin box at the left contains the SDR board. Note the fan in the top lid, which cools the ADC. Normally, this chip doesn't need forced air cooling, but since I can't attach any heatsink to the chip due to the way it has been mounted (see the November 2008 update above), forced air is the easiest solution.
In front, connected to the tin box via a BNC right-angle adapter, is a ninth-order low-pass filter for the receiver.
The board at the right contains the power amplifier, the RX/TX switch, and the transmit low-pass filter. The amplifier has two stages, a driver with an IRF511 mosfet followed by the final stage with an IRF510 (mounted on the black heatsink just left of the center of the board). Supplied with 30 volts, this delivers up to 20 watts on 7 MHz.

Between 9th and 11th of May, I let the hardware run with an FPGA configuration that allowed me to record the spectrum over the circuit's entire bandwidth, i.e., 0 through 37 MHz. The resulting waterfall display of this entire bandwidth during one and a half day looks as follows (click on it for the full picture, more than 3 MB):

Many things are notable, such as the day/night rhythm of propagation: mediumwave is good at night, whereas the higher bands are good during daylight. One clearly sees that the broadcast signals are by far the strongest, and can see that they are often switched on or off at the top of the hour. Note also that at 12:00 UTC activity on the 14 MHz amateur band suddenly increased: perhaps the start of a contest?

Update April 2013

I haven't updated this website for almost 4 years. That doesn't mean I'm not doing SDR thing anymore; to the contrary! However, not much new SDR hardware has been built. Much of the development has focussed on software, and in particular on the WebSDR project. Since the WebSDR is publicly visible, there's not much of a need to also tell here what I'm doing...

Anyway, here's a (probably incomplete) list of SDR-related things I've done over the past 4 years:

• Built a second and slightly different version of the November 2008 board for permanent use as a WebSDR.
• Installed that permanently at the university of Twente WebSDR site, allowing simultaneous tuning in 8 bands, using 8 DDCs in the FPGA firmware.
• Used the SDR with the 25 m Dwingeloo dish to make "moon photographs"; see here.
• Developed a GPU-based WebSDR, which together with appropriate firmware in my SDR board allows tuning in a much larger bandwidth, not restricted to the amateur bands: 9.7 MHz bandwidth initially (early 2010), 19.4 MHz later, and 29.1 MHz since summer 2012. The latter requires a rather awkward 3/4 decimation in the FPGA. The raw data stream out of the ADC, running at 77.76 MHz samplerate, is too much for the gigabit ethernet connection.
• Experimented with chirps reception; first using continuously tuning DDCs (in 2009), later integrating it with the wideband WebSDR to be able to receive all chirpsounders simultaneously.

Back to PA3FWM's amateur-radio page.