Understanding and enhancing Si5351 programming
Pieter-Tjerk de Boer, PA3FWM web@pa3fwm.nl(This is an adapted version of part of an article I wrote for the Dutch amateur radio magazine Electron, March 2025.)
The Si5351 is an integrated clock oscillator for digital (computer) systems. But it is also often found as a frequency synthesizer in amateur radio applications, such as transmitters and receivers, and test equipment such as the NanoVNA. Apparently, the signals generated by this chip are spectrally pure enough for this purpose. Furthermore, the frequency can be set in very small steps (less than a Hz), good enough for directly generating modulated signals such as WSPR and FT8. All of that is pretty surprising, given that the original application (clock signals) typically does not have such high demands. And such a chip costs only a few euros.
How does this chip manage to generate such pure signals, at such a high frequency resolution?
Together with Rick, PA1RVR, I have puzzled about this and done experiments on the actual chip;
on this page and the sequel
you find my observations, conclusions and conjectures.
And while doing this, we found a way to control the frequency in steps 128 times smaller
than promised by the chip's documentation; see below.
![[Si5351 block diagram]](tn42fig1.png)
Block diagram
The figure shows the chip's block diagram, copied straight from the datasheet [1]. At the left, it starts with a 25 or 27 MHz crystal oscillator (or, alternatively, an externally supplied reference frequency). This is used with a PLL to lock an oscillator (VCO) on a user-chosen frequency between 600 and 900 MHz. Next, that frequency is divided down by a user-set factor between 4 and 2000 (in the 'MultiSynth' block), resulting in a frequency between 0.3 and 200 MHz. In order to reach even lower output frequencies, there is a final divider (the 'R' block) which divides by a user-set power of 2, up to 27=128. The chip contains two such VCOs with PLLs, and three (or eight in other versions) output dividers. All their division and multiplication factors can be set independently for generating multiple simultaneous output signals.
What makes the chip special is the fact that both the PLL's multiplication factor,
and the division factor of the MultiSynth block, can be non-integer numbers.
![[Si5351 block diagram]](tn42fig2.png)
That allows setting the frequency in very small steps.
According to the datasheet, the factors must be of the form a+b/c,
where a, b and c are integers, with b<c and c<1048575.
Thus, the division factor is actually the integer a, with added to it a fraction b/c between 0 and 1.
Since c can be over a million,
the division factor can be set with six decimal digits in the fractional part (six digits after the decimal point).
Thus we arrive at the second block diagram,
where for clarity only a single VCO, PLL and output divider are shown.
Calculating the Si5351 divider factors
As noted above, the various Si5351 divider ratios are written in the form a+b/c, where a, b and c are integers. One would then expect that these integers are to be programmed into the chip, but that turns out not to be the case. Instead, one has to program three other numbers P1, P2 and P3 into the chip, and the manufacturer tells how those are to be calculated from a, b and c: [2](Floor means rounding down to an integer.)
To gain more understanding, we invert these formulas: instead of calculating what P1, P2 and P3 must be for a given division ratio a+b/c, we want to know what the resulting division ratio is for given P1, P2 and P3. After some puzzling, we arrived at the following expression:
Note how simple this formula is; in particular, all the Floor() stuff is gone! In fact, it just says P1+P2/P3, divided by 128 and plus 4.
Furthermore it is noteworthy that the stepsize has become 128 times smaller. Originally, the division ratio was set in steps of 1/c, and with the new formula the steps are 1/(128c) (since P3 equals c). That is odd: we now suddenly have, with exactly the same chip, much finer control of the frequency! There are many combinations of P1, P2 and P3 which will never come out of the original formulas, no matter what (integers) a, b and c are plugged in. But with our formula we can also calculate what the division ratio 'should be' for these 'impossible' combination of P1, P2 and P3. And we tried it in practice: such combinations indeed work as expected (if P2<P3); our formula is correct.
One wonders why the manufacturer didn't simply publish 'our' formula. Our formula is nearly as simple as a+b/c, saves the effort of converting a,b,c into P1,P2,P3, and gives 128 times smaller frequency steps for free. Actually, I'd also expect that we wouldn't be the first to find this formula and the extra frequency resolution, but we haven't seen them anywhere else yet.
In the sequel we use these insights to analyze further how the chip works.
References
[1] Si5351 datasheet: https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf[2] Application note AN619: https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
Text and images (except the first block diagram) on this page are copyright 2025, P.T. de Boer, web@pa3fwm.nl .
Republication is only allowed with my explicit permission.