Si5351 analysis and operation

Pieter-Tjerk de Boer, PA3FWM web@pa3fwm.nl

(This is an adapted version of part of an article I wrote for the Dutch amateur radio magazine Electron, March 2025.)

Fractional frequency dividers

As has become clear in the first part of this article, the Si5351 owes its enormous frequency resolution to the fact that its built-in frequency dividers are not limited to integer division ratios. But dividing a frequency by a non-integer is not easy. 'Normal' digital circuits, including frequency dividers, can only change their output signal at the moment an input signal changes. So dividing by 7 is simple: only pass every 7th input pulse on to the output. But dividing by 7.3 is not: one would need to generate an output impulse at a moment somewhere in between the 7th and 8th input impulse. If one does want to divide by such a non-integer, there are two possibilities:

(i) Be satisified with an approximation. Instead of really dividing by 7.3, divide by 7 most times, and by 8 occasionally, such that on average you're dividing by 7.3. Some output pulses will then be a bit early (when you've divided by 7 in that cycle), others will be a bit late (when you divided by 8): so there's a form of phase modulation or 'jitter' on the output signal.

(ii) Add extra (analogue) electronics to generate output pulses at those 'in between' moments. One could delay a pulse a bit by an analogue circuit, such as an RC network. Or the oscillator, from which the input signal comes, could have multiple outputs with different phase shifts, from which circuitry could choose one. Such a circuit for generating pulses at in-between moments, is called a 'phase interpolator'. If you want to divide by 7.3, you count 7 pulses, and then adjust the phase interpolator such that the next pulse is postponed by 0.3 times the period duration. If the phase interpolator is working correctly, there will be no phase modulation / jitter.

Analysis of the Si5351's fractional divider

Recall from the first part that the Si5351's divider ratios can be calculated as follows: $$\mathrm{division\; ratio}=\frac{\mathrm{P1}}{128}+\frac{1}{128}\cdot \frac{\mathrm{P2}}{\mathrm{P3}}+4$$

Looking at this formula, it is clear that the division ratio consists of two separate fractions. The first fraction has a fixed denominator of 128, but the numerator can be very large, up to 262143 (because P1 has 18 bits). The second fraction is 1/128 times P2/P3; it is very flexible in terms of numerator and denominator, but because P2<P3 its contribution is never more than 1/128.

Because of the prominent role of 1/128 in the formula, I suspect(ed) that the chip may have a phase-interpolator with 128 steps. The chip could use this to do the P1/128 division without jitter, using method (ii). Furthermore, the chip could do the fine tuning of the division ratio with P2/P3 using the approximation method (method (i)), switching back and forth between division ratios that differ by 1/128. If this suspicion is correct, it should be measureable: the output signal's phase should be 'jumping' with steps corresponding to 1/128 of the period of the VCO frequency (except when P2=0).

Experiment

With some effort we can indeed measure such phase steps. For this experiment I set the PLL multiplication factor to an integer, namely 25. With a 25 MHz crystal this results in the VCO running at 25 × 25 = 625 MHz. For the output divider, I set P1 = (271-4) × 128, P2=0 and P3=1000000. This sets the output division factor to 271, so the output signal is at 625 / 271 = 2.30627306273... MHz.

I fed this 2.306... MHz to my SDR, and I clocked the SDR from the same 25 MHz as the Si5351, so (temperature-induced) drift of this reference could not affect the measurement. In software I generated a signal of that same 625/271 = 2.306... MHz, and measured the phase difference between this and the received signal. In theory, this phase difference should be constant. The red line in the graph indeed shows that the phase difference is constant, except for some noise (measurement inaccuracy). For this graph I converted the phase difference to a time difference, by multiplying the phase difference by the duration of the 2.306... MHz period. Note how precise this measurement is: we're measuring picoseconds!

Next, I set P2 to 1. According to our formula, the 625 MHz is now no longer divided by 271, but by 271.0000000078125, resulting in an output frequency of 2.30627306266 MHz. That's only 66 µHz lower than before, about 1 period per 4 hours. I didn't change anything in the SDR and the software, so I was still measuring the phase difference w.r.t. the original frequency. If the signals were pure, we should see the phase drift gradually, 360 degrees per 4 hours.

But in practice we see something different: the blue line in the figure. Clearly, this is not a nice steady drift: the change is step-wise! (As we in fact suspected.) We see that the steps are about 6 ps each, and occur about 5 times per second.

The green line results from repeating the experiment with P2=2: we see the steps are equally large, but now occur twice as often.

Admittedly, the steps aren't very clear amidst the noise. That's why I repeated the experiment with setting P2 only briefly to 1, while keeping it at 0 the rest of the time. It turns out that if P2 is 1 for less than 0.2 seconds, the phase remains constant. But if it is set to 1 for slightly longer than 0.2 s, the phase does step. This threshold effect proves that if P2=1, the phase indeed changes stepwise. With this setup it is also possible to measure the size of the steps; taking the average of a large number of steps resulted in 6.25 ps (with 0.01 ps of statistical uncertainty).

Extra divide-by-2

Does the measured stepsize of 6.25 ps match our expecation? We expected the stepsize to be the VCO period divided by 128. The VCO is at 625 MHz, so its period is 1.6 ns, and 1/128 of that is 12.5 ps. Oops, that's (exactly) double what was measured! So apparently the chip does not work with 128 but with 256 steps.

And that should not come as a surprise. The datasheet promises that the output signal has a 50% duty cycle, and the easiest way to guarantee that is to put an extra divide-by-2 at the end. But in order to still get the expected division ratio despite the presence of that extra divide-by-2, the preceding fractional divider must have a half-as-large division ratio, and thus have steps of 1/256 instead of 1/128.

Conjectured block diagram

It's handy to split the 18 bits of P1 in two parts: we'll call the first 10 bits P1a, and the remaining 8 bits P1b. Together then P1 = 256×P1a + P1b. If we also take the extra divide-by-2 outside the parentheses, we get: $$\mathrm{division\; ratio}=2\times (\mathrm{P1a}+2+\frac{\mathrm{P1b}}{256}+\frac{1}{256}\cdot \frac{\mathrm{P2}}{\mathrm{P3}})$$

The next figure shows my conjecture (it's not more than that!) of how each a+b/c divider in the Si5351 may be realised. At the left we see the oscillator (VCO), directly followed by a 256-step phase-interpolator. I don't know how that phase-interpolator works, but it may well use multiple phase-shifted outputs from the VCO; hence multiple arrows connecting them. The phase-interpolator's output signal is fed to an integer divider which divides by P1a+2, followed by the fixed divide-by-2. As long as the phase-interpolator's setting is not changed, the output signal simply is the VCO divided by 2×P1a+4.

But there are two extra arrows, indicating when the phase-interpolator is advanced. The first such arrow comes from the P1a+2 divider: whenever there's a pulse here, we advance the phase-interpolator by P1b steps. Thus, the next pulse will arrive later by a fraction P1b/256 of the VCO's period, resulting in a non-integer contribution to the division ratio (method (ii)).

The second arrow goes via a P2/P3 divider. This block produces P2 output pulses for every P3 input pulses. Each output pulse advances the phase interpolator by 1 step, effectively increasing the P1 division by 1/256 for only the current cycle. This is method (i), toggling between two division ratios that differ by 1/256.

Spectral purity

Now that we (think we) understand how the chip works, we can also better estimate the spectral purity of its output signal.

If the phase interpolator is perfect, method (ii) in principle will not introduce phase noise. The only jitter then is due to method (i) with the P2/P3 contribution, i.e., due to switching back and forth between division ratios that differ by 1/256. Taking the VCO at 625 MHz as an example, the phase steps are 6.25 ps, so the maximum phase error is 3.125 ps. If the output frequency is 30 MHz, with a 33 ns period, then this phase error is 0.01 % of the full period: that gives a spurious signal which is about 80 dB below the carrier. At lower output frequencies this is (even) better accordingly. For comparison: without the phase interpolator the jitter would be 256 times larger, and the spurious suppressed by only some 30 dB.

However, it is too optimistic to assume that the phase interpolator is perfect. The figure shows the size of each of the 256 steps, as measured on my chip (for illustration, as the picture changes with the choice of division ratios and might also differ from one chip to the next). Most steps are pretty close to the expected value, but some are far too large or small.

The datasheet [1] also specifies the jitter: 'typical 70 ps', with the remark that this is a worst case figure and depends strongly on the configured frequencies. The fact that this is so much worse than expected based on the interpolator step size, presumably is due to 'analog' effects, such as crosstalk between the various parts of the chip, particularly if multiple outputs are active simultaneously.

References

[1] Si5351 datasheet: https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
[2] Application note AN619: https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf

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Text and images on this page are copyright 2025, P.T. de Boer, web@pa3fwm.nl .
Republication is only allowed with my explicit permission.